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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16654
150/154 OUTPUT TFT-LCD GATE DRIVE
The PD16654 is a TFT-LCD gate driver. Because this gate driver has a level shift circuit for logic input, it can output a high gate scanning voltage in response to a CMOS-level input. Moreover, it can also drive both the XGA/SXGA panel (154 outputs) and SVGA panel (150 outputs) by changing the number of outputs over between 150 and 154.
FEATURES
* High breakdown voltage output (ON/OFF range: VDD2-VEE2 = 40 V MAX.) * 3.3 V CMOS level input * Number of output select function (150/154 outputs)
ORDERING INFORMATION
Part Number Package TCP (TAB package)
PD16654N-xxx
The TCP's external shape is customized. To order your TCP's external shape, please contact an NEC salesperson.
Document No. S11647EJ1V0DS00 (1st edition) Date Published May 1998 N CP(K) Printed in Japan
(c)
1998
PD16654
1. BLOCK DIAGRAM
R/L Osel CLK LS LS LS
STVR OE1 OE2 OE3
LS LS LS LS
SR1 SR2 SR3
154-bit shift register
SR152 SR153 SR154
LS
STVL
O1
O2
O3
O152
O153
O154
LS (level shifter): Interfaces between 3.3 V CMOS level and VDD2-VEE1 level.
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PD16654
2. PIN CONFIGURATION (PD16654N-xxx xxx) xxx
S154 S153 S152 S151
VDD2 STVL OE1 OE2 OE3 CLK R/L VCC Osel VSS STVR VEE1 VEE2
(Cupper plated surface)
S4 S3 S2 S1
Caution This figure does not specify the TCP package.
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PD16654
3. PIN FUNCTIONS
Pin Symbol O1 to O154 Pin Name Driver output pins Description Scan signal output pins that drive the gate electrode of a TFT-LCD. The status of each output pin changes in synchronization with the rising edge of shift clock CLK. The output voltage of the driver is VDD2 to VEE2. Input/output pin of the internal shift register. Start pulse signal is read at the rising edge of shift clock CLK and a scan signal is output from the driver output pin. The interface of this terminal is CMOS of 3.3 V. When Osel signal is Low level, start pulse goes up to high level at the 154th falling edge of shift clock CLK and goes down to low level at the 155th falling edge. And when Osel signal is High level, start pulse goes up to high level at the 150th falling edge of shift clock CLK and goes down to low level at the 151st falling edge. The output level is VCC-VSS (logic level). Shift clock input for the internal shift register. The contents of internal shift register is shifted at the rising edge of CLK. Shift direction switching input pin of the internal shift register. R/L = H (right shift) : STVR O1 O2 *** O153 O154 STVL R/L = L (left shift) STVL O154 O153 *** O2 O1 STVR This pin fixes the driver output to the L level when it is high. However, the shift register is not cleared. And, output enable actuation is asynchronous in the clock. And, refer to "RELATIONS OF ENABLE INPUT AND OUTPUT TERMINAL". Selects the number of outputs. Osel = L : 154 outputs (SVGA) Osel = H: 150 outputs (VGA, XGA, SXGA) When Osel = H (150 outputs), O76 through O79 outputs of the shift register are fixed to the VEE2 level. Fix this pin to VCC (VDD2) or VSS (VEE1) on TCP. Shared with internal logic and driver 3.3 V 0.3 V. Reference power supply for level shifter: LS Connect this pin to the system ground. Negative power supply for internal logic
STVR STVL
Start pulse input/output pin
CLK
Shift clock input
R/L
Shift direction switching input
OE1 OE2 OE3
Enable input
Osel
Number of output select input
VDD2
Positive power supply for driver Reference power supply Ground (GND) Negative power supply for internal logic Negative power supply for driver
VCC VSS VEE1
VEE2
Negative power supply for driver
Caution 1. Power ON/OFF sequence To prevent the PD16654 from damage due to latch up, turn on power in the order VCC VEE1, VEE2 and VDD2 logic input. Turn off power in the reverse order. Observe these power sequences even during transition period.
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PD16654
Caution 2. Inserting bypass capacitor Because the internal logic operates at a high voltage (VDD2-VEE1), insert a bypass capacitor of about 0.1 F between the respective power pins as shown below to secure the noise margin of VIH and VIL.
VDD2 VCC 0.1 F VSS 0.1 F VEE2 VEE1 0.1 F 0.1 F
Do not input a switching signal to the Osel pin that selects the number of outputs. Connect this pin to VCC or VSS (VEE1).
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PD16654
4. RELATIONS OF ENABLE INPUT AND OUTPUT TERMINAL
Switching is possible for 154/150 with PD16654 by the Osel terminal. And, the output terminal which can be controlled by the enable signal changes as follows along with this function.
154 out TCP 154 out Mode (Osel = L) O1 (OE1) O2 (OE2) O3 (OE3) O4 (OE1) O5 (OE2) O6 (OE3) * * * O72 (OE3) O73 (OE1) O74 (OE2) O75 (OE3) O76 (OE1) O77 (OE2) O78 (OE3) O79 (OE1) O80 (OE2) O81 (OE3) O82 (OE1) * * * O150 (OE3) O151 (OE1) O152 (OE2) O153 (OE3) O154 (OE1) 150 out Mode (Osel = H) O1 (OE1) O2 (OE2) O3 (OE3) O4 (OE1) O5 (OE2) O6 (OE3) * * * O72 (OE3) O73 (OE1) O74 (OE2) O75 (OE3) Vout = VEE2 Vout = VEE2 Vout = VEE2 Vout = VEE2 O80 (OE1) O81 (OE2) O82 (OE3) * * * O150 (OE2) O151 (OE3) O152 (OE1) O153 (OE2) O154 (OE3) O80 (OE2) O81 (OE3) O82 (OE1) * * * O150 (OE3) O151 (OE1) O152 (OE2) O153 (OE3) O154 (OE1) O80 (OE1) O81 (OE2) O82 (OE3) * * * O150 (OE2) O151 (OE3) O152 (OE1) O153 (OE2) O154 (OE3) 150 out Mode 154 out Mode (Osel = L) O1 (OE1) O2 (OE2) O3 (OE3) O4 (OE1) O5 (OE2) O6 (OE3) * * * O72 (OE3) O73 (OE1) O74 (OE2) O75 (OE3) 150 out Mode (Osel = H) O1 (OE1) O2 (OE2) O3 (OE3) O4 (OE1) O5 (OE2) O6 (OE3) * * * O72 (OE3) O73 (OE1) O74 (OE2) O75 (OE3)
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PD16654
5. TIMING CHART
(1) 154 outputs, R/L = H Osel = L
1 CLK
2
3
153
154
155
156
157
OE1
OE2
OE3
STVR
O1
O2
O3
O153
O154
STVL
O1 of next stage O2 of next stage
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PD16654
(2) 150 outputs, R/L = H Osel = H
1 CLK
2
3
149
150
151
152
153
OE1
OE2
OE3
STVR
O1
O2
O3
O153
O154
STVL
O1 of next stage O2 of next stage
O76 to O79 is L (VEE2) level fixation (150 output).
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PD16654
6. ELECTRIC SPECIFICATION
Absolute Maximum Ratings (TA = 25C, VSS1 = VSS2 = 0 V)
Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Voltage Input Voltage Input Current Output Current Operating Temperature Range Storage Temperature Range Symbol VDD2 VCC VDD2-VEE1/2 VEE1 VEE2 VI II IO TA Tstg Rating -0.5 to +28 -0.5 to +7.0 -0.5 to 42 -16.5 to +0.5 VEE1 - 0.5 to +0.5 -0.5 to VCC + 0.5 10 10 -20 to +70 -55 to +125 Unit V V V V V V mA mA C C
Recommended Operating Condition (TA = -20 to +80C, VSS1 = VSS2 = 0 V)
Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Voltage Symbol VDD2 VEE1 VEE2 VDD2 - VEE1 VCC MIN. 17 -15 VEE1 22 3.0 3.3 TYP. MAX. 25 -5.0 VEE1 + 6.0 40 3.6 Unit V V V V V
Electrical Specifications (TA = -20 to +70C, VDD1 = 25 V, VDD2 = 3.3 V 0.3 V, VEE1 = VEE2 = -15 V, VSS = 0 V)
Parameter Input voltage, high Input voltage, low Output voltage, high Output voltage, low Output current, high Output current, low Output ON resistance Input leakage current Dynamic current Symbol VIH VIL VOH VOL InOH InOL Ron IIL IDD2 ICC IEE Condition CLK, STVR (STVL), R/L, Osel, OE1-OE3 STVR (STVL), IOH = -40 A STVR (STVL), IOL = +40 A On, Vn = VDD2 - 1.0 V On, Vn = VEE2 + 1.0 V Vn = VEE2 + 1.0 V or VDD2 - 1.0 V VI = 0 V or 3.6 V VDD2, fCLK = 30 kHz, no loads VCC1, fCLK = 30 kHz, no loads IEE1 + IEE2, fCLK = 30 kHz, no loads 1.0 1.0 1.0 400 600 800 MIN. 0.8 VCC VSS VCC - 0.4 VSS
Note Note
TYP.
MAX. VCC 0.2 VCC VCC
Note
Unit V V V
Note
VSS + 0.4 -1.0
V mA mA k
A A A A
Note The cascade output is at the driver level (VCC-VSS).
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PD16654
Switching Characteristics (TA = -20 to +70C, VDD1 = 25 V, VDD2 = 3.3 V 0.3 V, VEE1 = VEE2 = -15 V, VSS = 0 V)
Parameter Cascade output delay time Symbol tPHL1 tPLH1 Driver output delay time 1 tPHL2 tPLH2 Driver output delay time 2 tPHL3 tPLH3 Output rise time Output fall time Input capacitance Maximum clock frequency tTLH tTHL CI fmax. TA = 25C When connected in cascade 500 Condition CL = 20 pF CLK STVL (STVR) CL = 300 pF CLK On CL = 300 pF OEn On CL = 300 pF MIN. TYP. MAX. 800 800 500 500 500 500 450 450 15 Unit ns ns ns ns ns ns ns ns pF kHz
Timing Requirement (TA = -20 to +70C, VDD1 = 25 V, VDD2 = 3.3 V 0.3 V, VEE1 = VEE2 = -15 V, VSS = 0 V)
Parameter Clock Pulse Low Period Clock Pulse High Period Enable Pulse low period Data Setup Time Data Hold Time Symbol PWCLK(H) PWCLK(L) PWOE tSETUP tHOLD STVR (STVL) CLK CLK STVR (STVL) Condition MIN. 500 500 1.0 200 200 TYP. MAX. Unit ns ns
s
ns ns
The rise and fall times of logic input must be tr = tf = 20 ns (10% to 90%).
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PD16654
7. SWITCHING CHARACTERISTICS WAVEFORM (R/L = H)
1/fmax. PWCLK(H) PWCLK(L) VCC CLK 50% 50% 50% 50% VSS tSETUP tHOLD VCC STVL1/2 (STVR1/2) 50% 50% VSS tPLH1 tPHL1 VCC STVR1/2 (STVL1/2) 50% 50% VSS tPLH2 tTLH 90% tPHL2 90% tTHL VDD2
On
10%
10% VEE2 PWOE VCC
OEn
50%
50% VSS
tPLH3 VEE2
tPHL3 VDD2 90%
On VEE1 10% VEE1 VEE2
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PD16654
8. RECOMMENDED MOUNTING CONDITIONS
When mounting this product, please make sure that the following recommended conditions are satisfied. For packaging methods and conditions other than those recommended below, please contact NEC sales personnel.
Mounting Condition Thermocompression Mounting Method Soldering ACF (Adhesive Conductive Film) Condition Heating tool 300 to 350C, heating for 2 to 3 sec; pressure 100 g (per solder) Temporary bonding 70 to 100C; pressure 3 to 8 kg/cm ; time 3 to 5 sec. 2 Real bonding 165 to 180C; pressure 25 to 45 kg/cm , time 30 to 40 secs. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd.)
2
Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more packaging methods at a time. Reference NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades to NEC's Semiconductor Devices (C11531E)
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PD16654
[MEMO]
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PD16654
[MEMO]
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PD16654
[MEMO]
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PD16654
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96. 5

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